Introducing 2D-FETs in Device Scaling Roadmap using DTCO
Zubair Ahmed, Aryan Afzalian, T. Schram, Doyoung Jang, Devin Verreck, Quentin Smets, P. Schuddinck, Bilal Chehab, Surajit Sutar, Goutham Arutchelvan, Assawer Soussou, Inge Asselberghs, A. Spessot, Iuliana Radu, Bertrand Parvais, Julien Ryckaert, M. H. Na
Abstract
Superior electrostatic control of 2D-FETs enables continued logic power-performance-area (PPA) scaling beyond the 2nm node. Here, we show that WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based 2D devices give ~40% inverter performance boost against Si at imec 2nm node, using a process-aware DTCO approach. The DTCO is conducted based on an ab-initio calibrated, physical compact model while area scaling is based on contacted gate pitch scaling. Side contacted source/drain, vertically-stacked 2D sheets and fork-sheet architecture are highlighted as key enablers of 2D-FET technology for multiple advanced nodes, using experimentally realistic mobility and Schottky barrier height conditions.