FPGA implementation for 44.2368-Gbit/s PAM8 signal transmission with pruned pre-equalization
Yikai Wang, Yu Chen, Long Zhang, Sicong Xu, Kaihui Wang, Jianjun Yu
Abstract
In this experiment, we demonstrated an intensity modulation and direct-detection (IM/DD) system based on a field-programmable gate array (FPGA). The PAM8 signals are successfully delivered at 44.2368 Gbit/s over a 45-km standard single-mode fiber (SSMF), satisfying the soft-decision forward error correction (SD-FEC) criterion of 2.4 × 10 − 2 , and the net bit rate may reach 36.864 Gbit/s without the need of optical amplifiers. At the transmitter, we used a pruned pre-equalization algorithm to process the PAM8 signals, and the high-speed parallel PAM8 signals were processed at the receiver using 64 parallel constant modulus algorithm (CMA) and decision-directed least mean square (DD-LMS) equalizers. Additionally, we analyzed the bit error rate (BER) performance of the DD-LMS equalizer in FPGA simulation with various data lengths, both before and after equalization.