Optimization of low power 12 T SRAM bit cell using FinFET in 32 nm technology
Arijit Chakraborty, Ranjeet Singh Tomar, Mayank Sharma
Abstract
Over the duration of the evolution of the integrated circuit industry, the preference for optimizing the performance parameters of overall performance, power, delay, leakage, and time to market (opportunity cost) has not altered (IC enterprise). In truth, finding the most effective means of optimizing those parameters is at the heart of Moore's law. More than a third of tool settings were unable to be scaled any more, notably the voltage of the power source, which determines dynamic electricity. All aspects of power consumption, delay time, and efficiency of radiation protected SRAM cells are being studied in this research. Synopsys HSPICE is the finest backend device for analyzing SRAM's power consumption and delay. The results of the design and simulation of a 12 T SRAM in the 22 nm era utilizing FINFET technology are provided in this paper. The suggested circuit 12 t SRAM uses 99 percent less power, has a 99.7 percent higher power density, and uses 99 percent less energy.