Heterogeneous Power Delivery for Large Chiplet-based Systems using Integrated GaN/Si-Interconnect Fabric with sub-10 μm Bond Pitch
Haoxiang Ren, Krutikesh Sahoo, Ziyi Guo, Rishi Pugazhendhi, Zachary Wong, Tianyu Xiang, Timothy S. Fisher, Subramanian S. Iyer
Abstract
Power delivery and thermal dissipation are the Achilles heel of advanced packaging. Delivering power at high voltages minimizes IR drops and improves efficiency considerably. In this work, we present a wafer-level heterogeneous integration approach that enables the connection of wide bandgap GaN-on-Si high voltage (12-48 V) switches, controlled by a control chiplet, and capable of delivering up to 1Α/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at <1 V to a wafer-scale system using a segmented highly granular power delivery network (PDN). To mitigate parasitics, we employ a sub-10μm bond pitch dielet-to-interconnect fabric assembly with ALD Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> passivation, meeting stringent milspec standards for shear force, thermal cycling, and moisture ingress. Additionally, we demonstrate a dielet-side PDN that eliminates the need for through silicon vias (TSVs) and wafer thinning, resulting in significant cost and complexity reduction. It also frees up the backside of the high-thermal-conductivity and highly planar silicon for thermal dissipation. These developments will enable the manufacture of large-scale AI/ML systems beyond what is possible using classical silicon interposer technology.