Evolution of the Samsung Exynos CPU Microarchitecture
Brian Grayson, Jeff Rupley, Gerald Zuraski Zuraski, Eric Quinnell, Daniel A. Jiménez, Tarun Nakra, Paul Kitchin, Ryan Hensley, Edward Brekelbaum, Vikas Sinha, Ankit Ghiya
Abstract
The Samsung Exynos family of cores are highperformance “big” processors developed at the Samsung Austin Research & Design Center (SARC) starting in late 2011. This paper discusses selected aspects of the microarchitecture of these cores - specifically perceptron-based branch prediction, Spectre v2 security enhancements, micro-operation cache algorithms, prefetcher advancements, and memory latency optimizations. Each micro-architecture item evolved over time, both as part of continuous yearly improvement, and in reaction to changing mobile workloads.
Topics & Concepts
MicroarchitectureComputer scienceParallel computingBranch predictorCacheLatency (audio)Computer architectureArchitectureCAS latencyCoprocessorOperating systemCPU cacheInstruction setEmbedded systemMemory controllerSemiconductor memoryVisual artsArtTelecommunicationsParallel Computing and Optimization TechniquesAdvanced Data Storage TechnologiesInterconnection Networks and Systems