15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V<sub>MIN</sub> Applications
Jonathan Chang, Yen-Huei Chen, Gary Chan, Hank Cheng, Po‐Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li
Abstract
Despite recent advances, low-voltage operation remains one of the key approaches for power reduction. However, the continuous scaling of the SRAM bit cell, in advanced technologies, based on the transistor's minimum geometry is accompanied by increased random threshold voltage variations that limit the SRAM's minimum operating voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> ). The introduction of FinFET transistors has provided better short channel effects and less random dopant fluctuation, compared to prior bulk CMOS technology. However, the quantization of transistor sizing continues to be a major challenge for high-density 6T SRAM design. Figure 15.1.1(a) shows the layout of a high-density 6T SRAM bit cell in a 5nm EUV and high-mobility channel FinFET technology. In order to achieve a compact bit-cell area, using FinFET technology, all transistors have to consist of a single fin. Figure 15.1.1(b) shows the SRAM bit-cell area scaling trend since 2011: area continues to scale, even as technology evolved into the sub-20nm era. This work reports a 0.021 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> high-density SRAM bit cell for a leading edge 5nm technology [1]. Figure 15.1.2(a) shows the SRAM voltage scaling trend: where the blue line indicates the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> of the SRAM bit cell without circuit assist and the red line indicates the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> with circuit assist. Write assist is the key enabler for lowering V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> operation in 5nm technology. Figure 15.1.2(b) shows a contention between pull-up (PU) and pass-gate (PG) transistors during a write operation. A stronger PU transistor yields higher read stability, but it degrades the write margin significantly and results in a contention write V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> issue. In order to improve the write V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> , the negative BL (NBL) and lower cell V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> (LCV) techniques have been proposed [2], [6]. However, the write-assist circuitry results in area overhead. In order to reduce the area of the assist circuitry, this work proposes NBL [7] and LCV with metal coupling/charge sharing capacitors to reduce the area overhead of the NBL-boosted and LCV charge-sharing capacitors. Furthermore, the flying BL (FBL) architecture [8] is also implemented to further reduce area.