FPGA Real-Time Deployment of Low-Complexity Volterra Equalizer Based on Pruning and Non-Uniform Quantization
Xinda Sun, Kaihui Wang, Zonghui Zhu, Long Zhang, Yumeng Gou, Yuanxiao Meng, Yun Chen, Jianjun Yu
Abstract
Electronic nonlinear equalization technology is a promising signal impairments compensation technique with great development potential and wide application scenarios. However, its high complexity makes it challenging to implement in field-programmable gate array (FPGA). We propose a low-complexity real-time nonlinear equalization scheme based on FPGA, which can provide similar performance as traditional schemes but only occupies very low digital signal processing (DSP) resources. With the help of this scheme, by using pruning and non-uniform quantization, the computational complexity of a Volterra equalizer with 15 linear taps and 25 nonlinear taps is comparable to that of a Volterra equalizer with 8 linear taps and 4 nonlinear taps. By non-uniformly quantizing the taps of the equalizer, the quantization accuracy can be saved compared to uniform quantization, and after the taps are quantized, complex multiplication can be replaced by simple shift operations, simplifying the complexity of multiplication operations. The scheme of weight pruning and non-uniform quantization significantly reduces the required hardware resources and power consumption. We verify the proposed scheme in a decision-directed Volterra (DD-Volterra) equalizer, The equalizer was successfully deployed in a 230.4 MHz xcvu9pflgb2104-2-I Xilinx FPGA and achieved real-time IM/DD transmission of 29.4912 Gbit/s PAM4 signals over 25 km standard single-mode fiber (SSMF), meeting the 3.8 × 10-3 hard-decision forward error correction (HD-FEC) standard. The results show that the proposed low-complexity Volterra equalizer scheme can reduce DSP resources by up to 75.3% and power consumption by 26.2%.