A 20-GHz PLL With 20.9-fs Random Jitter

Abstract

This article describes an integer- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL) that incorporates a phase detector sampling both the rising and falling edges of the reference clock. The circuit also uses a new retiming method in the feedback divider. Optimized for the reference and oscillator phase noise and fabricated in the 28-nm CMOS technology, the experimental prototype achieves an rms jitter of 20.9 fs integrated from 10 kHz to 40 MHz with a spur level of −66 dBc while consuming 12 mW of power.

Topics & Concepts