Performance and Short-Circuit Reliability of SiC MOSFETs With Enhanced JFET Doping Design
Chaobiao Lin, Na Ren, Hongyi Xu, Kuang Sheng
Abstract
In this article, the influence of the JFET width and JFET doping concentration on the 1.2-kV planar-gate silicon carbide (SiC) MOSFETs’ static characteristics, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics, and short-circuit (SC) reliability is discussed. With the increase of the JFET width, the specific ON-resistance decreases first and then increases (but the quasi-saturated current continues to increase), the blocking voltage decreases, and the reverse capacitance increases. The SC tests under 400-V dc bus voltage are carried out to compare the SC capability of the devices. With the increase of the JFET width, the SC peak current first increases and then decreases, and the SC withstanding time keeps decreasing. The increase of peak current is due to the weaker electric field shielding effect by the P-well. With the further increase of the JFET width, the peak current decreases because the depletion layer appears in the middle position of the JFET region below the gate oxide and the channel density decreases with the wider JFET width. Compared with the winner of the traditional design, the winner with enhanced JFET doping is preferred because it achieves an increased Baliga’s figure of merit (BFOM) by 15.9% and 1/high-frequency figure of merit (HF-FOM) by 84.2% without sacrificing too much SC reliability, which is more competitive.