Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-Implantable Microsystems
Fereshteh Kalantari, Hossein Hosseini‐Nejad, Amir M. Sodagar
Abstract
This article proposes an unsupervised online spike sorter, dedicated to brain-implantable neural recording microsystems. The main (online) spike sorting phase in the proposed approach is based on the wave shape resemblance between spike classes, realized by template matching. This phase follows an offline training phase, implemented off the implant. In the training phase, the number and centroids of the clusters are automatically determined and subsequently sent to the implant to configure the on-implant online spike sorter. Comprehensively verified using two separate datasets with a wide spectrum of spike wave shapes, the proposed approach presents average classification accuracies of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 85$ </tex-math></inline-formula> % (unsupervised) and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 92$ </tex-math></inline-formula> % (supervised). A 64-channel spike sorter was designed using a computational core with folded architecture. To make the very large-scale integration (VLSI) implementation of this spike sorter appropriate for brain implants in terms of both power and area consumption, the computations realizing the proposed approach were significantly reduced. Designed in a standard 180-nm CMOS technology, the circuit consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.74~\mu \text{W}$ </tex-math></inline-formula> /channel and per-channel area of 0.047 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The circuit is capable of clustering neural spikes in real-time with a latency of as short as 1.36 ms. A prototype of the circuit was implemented and successfully tested.