A Low-Latency FPGA Implementation for Real-Time Object Detection
Jinming Zhang, Lifu Cheng, Cen Li, Yongfu Li, Guanghui He, Ningyi Xu, Yong Lian
Abstract
The advancement of object detection algorithms makes them widely used in autonomous systems. However, due to high computational complexity of Convolutional Neural Networks(CNN), stringent latency requirement is hard to meet for real-time object detection. To address this problem, a low-latency accelerator architecture is proposed in this paper. A fine-grained column-based pipeline architecture with padding skip technique is implemented to reduce the start-up time of pipeline. In order to cut down the computational time of CNN, double signed-multiplication correcting circuit is introduced. In addition, pooling unit with share buffer is proposed to reduce storage cost for pooling layer. To demonstrate our new architecture, we implement the YOLOv2-tiny deep neural network (you-only-look-once) with input size 1280×384 on ZC706 development board, improving the latency by 2.125× to 2.34× compared to previous FPGA accelerator for YOLOv2-tiny.