Novel 4F<sup>2</sup> Multi-Bit Dual-Gate 2T0C for High-Density DRAM with Improved Vertical-Channel IGZO TFTs by Self-Aligned Single-Step Process
Fuxi Liao, Zhengyong Zhu, Kaifei Chen, Guanhua Yang, Menggan Liu, Wendong Lu, Zijing Wu, Jiebin Niu, Congyan Lu, Bok-Moon Kang, Jinghong Shi, Xie-Shuai Wu, Richeng Yu, Weidong Zhang, Jing Zhang, Guilei Wang, Jinshan Yue, Jiawei Wang, Lingfei Wang, Di Geng, Nianduan Lu, Chao Zhao, Arokia Nathan, Ling Li, Ming Liu
Abstract
For the first time, we propose and experimentally demonstrate one novel 4<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F2</sup> vertical-channel IGZO multi-bit dual-gate (DG) 2T0C. Contrary to the sequential integration in single-gate (SG) 4<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F2</sup>2T0C, vertical-channel IGZO DG write and read transistors in 4F<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 2TOC are integrated simultaneously by adopting self-aligned single-step (SASS) process. This integration process is not only cost-effective but also releases the typical misalignment, thermal cycling and contamination issues. By this design, the vertical-channel IGZO DG devices show record-high ION of 45.5 f.1A/μm -VTH+1V&VDs=lV and low SS of 68 mV/dec. The 4<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F2</sup>DG 2TOC cell provides reliable read/write operation with high current ratio of IDATA1/IDATAo>300 and long retention time (>470s). Multi-bit storage (2 bit) is also demonstrated for further increasing storage density in this ultra-scaled 4F<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell. This work shows a great prospect for high-density 2TOC DRAM.