High-Performance Latch Designs of Double-Node-Upset Self-Recovery and Triple-Node-Upset Tolerance for Aerospace Applications
Chunyu Peng, Lang Tian, Licai Hao, Qiang Zhao, Chenghu Dai, Zhiting Lin, Xiulong Wu
Abstract
With the advancement of integrated circuit technology, nanoscale latches operating in space environments are more sensitive to single-event mutiple-node-upset. Based on polarity design, this paper proposes a N-polarity cell(N-cell) and a Ppolarity cell(P-cell) which can block the propagation of doublenode-upset(DNU). Then, a low-overhead DNU self-recoverable latch(LODRL) is proposed which consists of a DNU self-recoverable core structure(DNUR core) and a clock-gated inverter. Compared with state-of-the-art DNUR latches, the proposed LODRL has average reduction of 17.07%, 52.62%, 31.23%, and 78.81% in area, power consumption, delay, and PDAP, respectively. Furthermore, a high-performance DNU self-recoverable and TNU tolerant latch(DRTTL) is proposed, which consists of a DNUR core, a clockgated inverter, and an interlocked structure.Compared with these advanced TNU tolerant(TNUT) latches, the DRTTL has an average reduction in power consumption, delay, and PDAP of 17.7%, 41.91% and 56.25%, respectively. The DRTTL is also insensitive to high-impedance-state and PVT variations, exhibits a large critical charge, and can achieve complete DNU self-recovery and 90% TNU self-recovery. Therefore, the DRTTL features low overhead and high performance, which is suitable for applications in aerospace environments.