uiCA
Andreas Abel, Jan Reineke
Abstract
Performance models that statically predict the steady-state throughput of basic blocks on particular microarchitectures, such as IACA, Ithemal, llvm-mca, OSACA, or CQA, can guide optimizing compilers and aid manual software optimization. However, their utility heavily depends on the accuracy of their predictions. The average error of existing models compared to measurements on the actual hardware has been shown to lie between 9% and 36%. But how good is this? To answer this question, we propose an extremely simple analytical throughput model that may serve as a baseline. Surprisingly, this model is already competitive with the state of the art, indicating that there is significant potential for improvement.
Topics & Concepts
Computer scienceBenchmark (surveying)MicroarchitecturePipeline (software)ThroughputCompilerSuiteParallel computingSoftwareComputer engineeringComputer architectureProgramming languageOperating systemGeodesyHistoryArchaeologyWirelessGeographyParallel Computing and Optimization TechniquesAdvanced Data Storage TechnologiesSemiconductor materials and devices