Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays
Subhali Subhechha, Stefan Cosemans, Attilio Belmonte, Nouredine Rassoul, Shamin Houshmand Sharifi, Peter Debacker, Diederik Verkest, Romain Delhougne, Gouri Sankar Kar
Abstract
We report on the first demonstration of multilevel multiply accumulation operations in 2TlC cell arrays based on amorphous IGZO TFTs for efficient analog in memory compute (AiMC) implementation. Device designs for the read and write transistors to meet the target specifications are discussed and implemented. Multilevel operations are realized thanks to the long retention time enabled by the ultra-low offcurrent (<1.5× 1$0^{-19}$A/$\mu$m) of the a-IGZO TFTs.
Topics & Concepts
TransistorThin-film transistorComputer scienceOptoelectronicsMaterials scienceElectronic engineeringElectrical engineeringNanotechnologyEngineeringVoltageLayer (electronics)Thin-Film Transistor TechnologiesAdvanced Memory and Neural ComputingSemiconductor materials and devices