A High-Efficiency D-Band Frequency Doubler in 22-nm FDSOI CMOS
Matthias Möck, İbrahim Kağan Aksoyak, Ahmet Çağrı Ulusoy
Abstract
This paper presents a high-efficiency D-band push-push frequency doubler implemented in 22-nm FDSOI CMOS technology. A 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> harmonic load-pull approach is followed, and a maximum output power of 4.1 dBm is achieved at 135 GHz while the circuit consumes only 24.7 mW from a 800 mV supply. The conversion gain peaks at -3.8 dB with a 3-dB bandwidth of 125–145 GHz (14.9%). The measured peak DC-to-RF efficiency and total efficiency values are 11.8 % and 9.1% respectively, which presents to the authors' best knowledge a leading-edge performance among the reported active CMOS frequency doublers at this frequency range.