A 40-nm 202.3nJ/Classification Neuromorphic Architecture Employing In-SRAM Charge-Domain Compute
Chang Liu, Zihao Xuan, Yi Kang
Abstract
In recent years, temporal neural network (TNN) emerges as a promising direction of development of spiking neural network (SNN) for low power applications. This paper proposes a compact digital-analog hybrid SRAM in-memory computing TNN architecture and circuits, using bionic low-power spike communication and the synaptic array operation based on charge domain computing. Simulation shows the proposed circuits achieve 94.73% accuracy on MNIST hand-written character recognition, consume only 202.3nJ per inference, and occupy a small area of 0.6mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
Topics & Concepts
Neuromorphic engineeringMNIST databaseStatic random-access memoryComputer scienceDomain (mathematical analysis)Spiking neural networkArtificial neural networkElectronic circuitComputer architecturePower (physics)InferenceSpike (software development)ArchitectureArtificial intelligenceElectronic engineeringComputer hardwareElectrical engineeringEngineeringMathematicsPhysicsQuantum mechanicsMathematical analysisVisual artsArtSoftware engineeringAdvanced Memory and Neural ComputingNeural dynamics and brain functionFerroelectric and Negative Capacitance Devices