An Efficient Detector for Massive MIMO Based on Improved Matrix Partition
Huizheng Wang, Yahui Ji, Yifei Shen, Wenqing Song, Muhao Li, Xiaohu You, Chuan Zhang
Abstract
Massive multiple-input multiple-output (M-MIMO) brings better robustness and spectral efficiency but higher computational challenges compared to small-scale MIMO. One of the key challenges is the large-scale matrix inversion, as widely employed in channel estimation and detection. Traditionally, to address the issue, several low-complexity matrix inversion methods have been proposed, including the tri-diagonal matrix approximation (TMA) and the Neumann-series approximation (NSA). Although the previous methods effectively alleviate the computational cost, they all fail to exploit the typical properties of channel matrices, leading to unsatisfactory error-rate performance in some non-ideal scenarios. To solve the issue, in this paper, a two-level and block diagonal based improved Neumann series approximation (TL-BD-INSA) algorithm is proposed, which is suitable for both ideal uncorrelated channels and the correlated channels with multiple-antenna user equipment (MAUE) system. First, a two-level block diagonal iteration based on matrix partition is employed, which exhibits performance comparable to the exact method while having a lower computational load. An improved normalization factor is then introduced to accelerate convergence. Numerical results show that, for 128×32 MIMO with MAUE non-ideal channel, the proposed algorithm performs only 0.25 dB away from the exact matrix inversion when bit error rate (BER) = 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . The implementation on Xilinx Virtex-7 FPGA and ASIC with TSMC 45 nm shows that the proposed detector can achieve 1731 bps/slices and 0.463 Gbps/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> hardware efficiency, respectively, demonstrating that the proposed system can achieve a well trade-off between error performance and implementation efficiency.