A Time-Interleaved Digital-to-Analog Converter up to 118 GS/s With Integrated Analog Multiplexer in 28-nm FD-SOI CMOS Technology
Daniel Widmann, Tobias Tannert, Xuan-Quang Du, Thomas Veigel, Markus Grözing, Manfred Berroth
Abstract
To enhance sampling rates of CMOS digital-to-analog converters (DACs), analog multiplexing of several DAC output signals in the time domain provides a solution. In this article, a full CMOS integration of two sub-DACs and an active analog multiplexer (AMUX) on a single chip in 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology is presented for the first time for sampling rates of 100 GS/s and beyond. Sampling rates up to 108 GS/s for broadband pulse-amplitude modulated (PAM) signals and up to 118 GS/s for oversampled signals are shown outperforming previously reported data in terms of sampling rate or data rate, respectively. Two 8-bit sub-DACs up to 59 GS/s with CMOS inverter-based output drivers and pseudo-segmentation provide the analog input data for the 2:1 AMUX realized in current-mode topology. An additional on-chip memory of 256 kB completes the system to a universal arbitrary waveform generator (AWG). At 100 GS/s, the total power consumption is about 4 W. Generally, an AMUX is able to shift the limits of DACs in well-established CMOS technologies toward higher frequencies independent on technology advances and opens a second, conceptual path for achieving higher sampling rates with an additional benefit of a principle bandwidth extension by the AMUX operation.