Tailoring the transfer characteristics and hysteresis in MoS<sub>2</sub> transistors using substrate engineering
P. Shiva Prasad, M.O. Garg, U. Chandni
Abstract
We demonstrate a novel form of transfer characteristics in substrate engineered MoS2 field effect transistors. Robust hysteresis with stable threshold voltages and a large gate voltage window is observed, which is suppressed at low temperatures. We analyse the dependence of the device characteristics on gate voltage range, gate stressing and sweep rates. We infer that the hysteresis originates from artificially created charged traps near the MoS2-SiO2 interface. These charge traps act as long range Coulomb scatterers and are screened at high carrier densities. The hysteresis is strongly suppressed in measurements on wafers devoid of the substrate treatment, providing a new extrinsic route to carefully tune the transfer characteristics.