A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL With −78.7-dBc REF Spur, −128.1-dBc/Hz Absolute In-Band PN and −254-dB FOM
Zunsong Yang, Yong Chen, Pui‐In Mak, Rui P. Martins
Abstract
This letter presents a type-I narrow-pulse-sampling (NPS) phase-locked loop (PLL). It features a circuit technique: NPS phase detector + T-shape switch, to address the main spur-related nonidealities. Fabricated in 28-nm CMOS, the NPS-PLL operating at 3.3-GHz measures a -78.7-dBc reference spur and a -128.1-dBc/Hz absolute in-band phase noise at 1-MHz offset for a jitter-power figure-of-merit (FOM) of -254 dB, without the need of calibration and reference buffer.
Topics & Concepts
dBcJitterPhase-locked loopPhase noiseMaterials scienceOffset (computer science)CMOSOptoelectronicsSampling (signal processing)Electrical engineeringDetectorEngineeringComputer scienceProgramming languageAdvancements in PLL and VCO TechnologiesRadio Frequency Integrated Circuit DesignElectromagnetic Compatibility and Noise Suppression