Power-Efficient CMOS Cellular RF Receivers for Carrier Aggregation According to RF Front-End Configuration
Youngmin Kim, Junghwan Han, Jae‐Seung Lee, Taehwan Jin, Pilsung Jang, Heeseon Shin, Jongwoo Lee, Thomas Byunghak Cho
Abstract
This article presents power-efficient radio frequency (RF) receiver designs, particularly for advanced long-term evolution cellular applications. The two proposed single-ended receiver architectures can fully support multiple-channel RF signals in advanced carrier aggregation (CA) scenarios with maximum design flexibility depending on the RF front-end module configuration and target applications. Two different low-noise amplifier (LNA) topologies are employed in receivers to achieve different bandwidth handling capabilities and linearity requirements. The first receiver architecture utilizes narrowband LNAs with a current-reusing technique using a 28-nm low-power complementary metal-oxide-semiconductor (CMOS) technology. The proposed receiver with this single-ended narrowband LNA can handle up to three carrier components (CCs) CA. The second receiver architecture shows wideband characteristics and employs current-efficient and high linear wideband LNAs. This proposed design can support up to five CC CA and is implemented in a 14-nm Fin field-effect-transistor CMOS technology. Moreover, frequency-band switchable transformers are utilized in both designs to realize size-efficient receivers. Both proposed receivers operate at a frequency ranging from 0.6 to 2.7 GHz. The implemented narrowband and wideband receivers have conversion gains exceeding 70 and 62 dB, and achieve noise figures of less than 3.5 and 5 dB during all CA scenarios, respectively. The proposed receivers operate at a nominal supply of 1.2 and 1.0 V for 28 and 14-nm CMOS technologies, respectively.