Trench Shielded Planar Gate IGBT (TSPG-IGBT) With Self-Biased pMOS Realizing Both Low On-State Voltage and Low Saturation Current
Rongxin Chen, Bo Yi, Xingbi Chen
Abstract
A novel trench shielded planar gate IGBT (TSPG-IGBT) with self-biased pMOS is proposed in this paper. It features a P-layer beneath the trench of the TSPG-IGBT to form a self-biased pMOS, which provides an additional path for the hole current and clamps the potential of the nMOS's intrinsic drain for lower saturation current. In the off-state, with the increasing potential of the N-cs (N-doped carrier store layer), the self-biased pMOS turns on and the potential of the P-layer will be clamped by the hole channel. Then, the reverse voltage is sustained by the P-layer/N-drift junction and the potential of the N-cs is shielded by the clamped P-layer region. Therefore, the N-cs can be heavily doped to reduce the on-state voltage (Von) without decreasing the breakdown voltage. Compared with the conventional TSPGIGBT, the Von of the proposed TSPG-IGBT is reduced by 0.3 V at the current density of 200 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with the same turn-off loss. Besides, the saturation current density of the proposed one is decreased by 24%.