Negative Gate Bias Induced Dynamic ON-Resistance Degradation in Schottky-Type <i>p</i>-Gan Gate HEMTs
Zuoheng Jiang, Mengyuan Hua, Xinran Huang, Lingling Li, Chengcai Wang, Junting Chen, Kevin J. Chen
Abstract
In this article, the impacts of the <small>off</small>-state gate bias (<i>V</i><sub>GS,OFF</sub>) on dynamic <small>on</small>-resistance (<i>R</i><sub>ON</sub>) are systematically investigated in commercial Schottky-type <i>p</i>-GaN Gate high-electron-mobility transistors. Double-pulse tester and pulsed <i>I</i>–<i>V</i> system are adopted to evaluate the dynamic <i>R</i><sub>ON</sub> with various <small>off</small>-state gate and drain bias (<i>V</i><sub>DS,OFF</sub>) under hard- and soft-switching conditions. More negative <i>V</i><sub>GS,OFF</sub> can aggravate the dynamic <i>R</i><sub>ON</sub> degradation under both soft- and hard-switching, especially when switching with a high <i>V</i><sub>DS,OFF</sub>. The impacts of <i>V</i><sub>GS,OFF</sub> on switching transients and <small>off</small>-state stress are investigated separately to reveal the underlying mechanisms, which are found to be associated with the generation and movements of holes. The <small>off</small>-state gate bias of the voltage-driving scheme needs to be carefully considered according to the identified mechanisms in terms of dynamic <small>on</small>-resistance degradation.