Design and development of a novel MOSFET structure for reduction of reverse bias pn junction leakage current
Debasis Mukherjee, B.V. Ramana Reddy
Abstract
Present world is acquainted with the plethora of battery operated portable electronic goods in leaps and bounds. For long life of battery, it is very imperative to minimise the leakage current in devices. Amount of leakage in scaled deep-submicron VLSI 1 CMOS circuitry has already occupied a momentous part of the total power consumption, and likely to amplify in future with technology scaling. Top three dominant components of transistor leakage current are gate leakage, subthreshold leakage and p-n junction leakage. We report our study of constructional modification of MOSFET transistor to control p-n junction leakage current. TCAD simulation was performed on a 20 nm NMOS, following the rules of International Technology Roadmap for Semiconductors (ITRS). As substrate is the common terminal for this kind of leakage, substrate current was measured to note the effectiveness of the proposed methodology. A 52% reduction in substrate leakage current was noted after applying the proposed methodology.