Monolithically Stacked Two Layers of a-IGZO-Based Transistors Upon a-IGZO-Based Analog/Logic Circuits

Abstract

In this work, back end of line (BEOL)-compatible amorphous indium–gallium–zinc oxide (a-IGZO) transistors are monolithically stacked on top of first-layer a-IGZO-based analog/digital circuits, including a single-stage amplifier and a five-stage ring oscillator (RO). The second-layer a-IGZO transistors are fabricated with a low thermal budget ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 200~^{\circ }\text{C}$ </tex-math></inline-formula> ), demonstrating an ultralow subthreshold swing of 75.7 mV/dec, ultralow leakage current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 10^{-{12}}$ </tex-math></inline-formula> A), and ultrahigh ON/OFF ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{9}}$ </tex-math></inline-formula> ). After 3-D integration, the performance of a-IGZO-based amplifiers and RO circuits in the first layer shows negligible degradation and exhibits a maximum voltage gain larger than 100 at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {DD}}} =10$ </tex-math></inline-formula> V and a maximum oscillation frequency of 3.3 kHz at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {DD}}} =5.5$ </tex-math></inline-formula> V. This work proves that a-IGZO-based transistors and circuits can be monolithically stacked without performance degradation and shows great prospects for potential high-density and high-performance monolithic 3-D integration applications.

Topics & Concepts