Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node
Deepak Mittal, V. K. Tomar
Abstract
In this paper, various SRAM cell topologies have been implemented on 90nm technology node with Cadence virtuoso tool. Read power and write power dissipation, read delay, write delay, write static noise margin (WSNM) and read static noise margin (RSNM) of all considered topologies have been determined out. Read and write actions of each SRAM cells have also been examined. It has been noticed that 7T SRAM cell has minimum read power among all considered topologies. However, write power in 8T SRAM cell reduced by 44.15% as correlated to conventional 6T SRAM cell. The write delay in 9T SRAM cell found minimum among all considered cells. Furthermore, highest value of RSNM has been observed in conventional 6T SRAM cell as correlated to all simulated topologies. The WSNM of 8T SRAM cell found to 2× as of 6T SRAM cell.