A multiple negative differential resistance heterojunction device and its circuit application to ternary static random access memory
Kwan-Ho Kim, Hyung‐Youl Park, Jaewoo Shim, Gicheol Shin, Maksim Andreev, Jiwan Koo, Gwangwe Yoo, Kil‐Su Jung, Keun Heo, Yoonmyung Lee, Hyun‐Yong Yu, Kyung Rok Kim, Jeong Ho Cho, Sungjoo Lee, Jin‐Hong Park
Abstract
For increasing the restricted bit-density in the conventional binary logic system, extensive research efforts have been directed toward implementing single devices with a two threshold voltage (VTH) characteristic via the single negative differential resistance (NDR) phenomenon. In particular, recent advances in forming van der Waals (vdW) heterostructures with two-dimensional crystals have opened up new possibilities for realizing such NDR-based tunneling devices. However, it has been challenging to exhibit three VTH through the multiple-NDR (m-NDR) phenomenon in a single device even by using vdW heterostructures. Here, we show the m-NDR device formed on a BP/(ReS2 + HfS2) type-III double-heterostructure. This m-NDR device is then integrated with a vdW transistor to demonstrate a ternary vdW latch circuit capable of storing three logic states. Finally, the ternary latch is extended toward ternary SRAM, and its high-speed write and read operations are theoretically verified.