The SALT—Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment
Carlos Abellán Beteta, D. Andreou, M. Artuso, A. Beiter, S. Blusk, Roma Bugiel, S. Bugiel, A. Carbone, T. Carli, Bo Chen, Nadim Conti, Federico de Benedetti, S. Ding, S. Ely, M. Firlej, T. Fiutowski, P. Gandini, D Germann, Nathan Allen Grieser, M. Idzik, X. Jiang, W. Krupa, Yiming Li, Z. Li, X. Liang, Shuaiyi Liu, Y. Lu, Lauren Grace Mackey, J. Moroń, R. Mountain, M. Petruzzo, H. Pham, B. Schmidt, S. Sheng, E. Spadaro Norella, K. Świentek, T. Szumlak, M. Tobin, Jianchun Wang, M. Wilkinson, H. Wu, Feihao Zhang, Q. Zou
Abstract
SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.