Gate Drive Circuit Implementation for Parallel Connection of Power Devices Considering Parasitic Inductance
Yudai Funaki, Keiji Wãda
Abstract
SiC devices are potential future power devices because of their higher switching speed and lower ON resistance than those of Si devices. Research and development efforts to apply them in medium- and large-capacity power conversion circuits are underway. However, SiC power devices in TO packages, which are general-purpose packages, are difficult to apply in high-current applications owing to their low current ratings. Therefore, increasing the capacity of power devices by connecting them in parallel is being studied. However, the current imbalance during switching due to the differences in device characteristics and variations in parasitic inductance is problem. This study proposed a current-balancing procedure focused on the parasitic inductances around power devices and gate drive circuit implementation. The proposed method was verified by conducting double-pulse tests at 300V and 200A.