A 68.6fs<sub>rms</sub>-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching
Simone M. Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
Abstract
To pursue the ever-growing trend in mobile data-rates, modern transceivers exploit carrier aggregation and high-order modulations, at the price of calling for ultra-low jitter (below 100fs) and frequency-agile local oscillators. Although the bang-bang digital-PLL (BBPLL) architecture can meet the stringent 5G jitter requirements at low power consumption and silicon area [1], its inability to quickly recover from a frequency jump, caused by the narrow linear range of a bang-bang phase detector (BBPD), has so far prevented its application when frequency agility is an important requirement. A high-resolution and wide-range time-to-digital converter (TDC), rather than a BBPD, would solve this issue at the price of larger power and area. As a matter of fact, fast-hopping ADPLLs using multibit TDCs have been demonstrated in applications with relaxed jitter specifications [2], [3]. To break the trade-off between frequency agility and jitter-power product, auxiliary frequency-acquisition loops have been recently adopted in BBPLL architectures [1], [4], [5]. Those auxiliary loops, based on extra BBPDs, control the digitally-controlled-oscillator (DCO) frequency with a gain larger than that of the main loop, thus decreasing the settling time. Unfortunately, above a certain control-gain value, the system nonlinearity introduces an unwanted dependence between the main and auxiliary loops, limiting locking time to several thousands of reference cycles.