Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks
Meizhi Wang, V Iyer, Shanshan Xie, Ge Li, Sanu Mathew, Raghavan Kumar, Michael Orshansky, Ali E. Yılmaz, Jaydeep P. Kulkarni
Abstract
We present physical design strategies viz. (i) power grid shielding, (ii) power grid twisting, (iii) increased local decoupling capacitors with VSS shields, and (iv) isolated S-Box module placement to improve the resilience of the Advanced Encryption Standard (AES-128) cryptographic core against fine-grained electromagnetic (EM) side-channel analysis (SCA). Localized EM field measurements are performed using a 0.5 mm radius H-field probe on 3 different, 40nm CMOS test-chips implementing 9 physical design configurations of the AES core. These physical design strategies show 2.45x, 1.51x, 2.61x, and 2.71x higher measurements to disclosure (MTD) respectively compared to the baseline design without incurring any power overhead. These strategies can be applied independently or optimally combined further improving fine-grained EM SCA resilience.