Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism
Mahyar Emami, Sahand Kashani, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus
Abstract
The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware depend heavily upon cycle-accurate simulation of register-transfer-level (RTL) designs. The fastest software RTL simulators can simulate designs at 1--1000 kHz, i.e., more than three orders of magnitude slower than hardware. Improved simulators can increase designers' productivity by speeding design iterations and permitting more exhaustive exploration.
Topics & Concepts
Computer scienceLogic simulationRegister-transfer levelParallel computingSoftwareParallelism (grammar)Computer architectureEmbedded systemLogic synthesisComputer hardwareLogic gateAlgorithmOperating systemEmbedded Systems Design TechniquesVLSI and FPGA Design TechniquesInterconnection Networks and Systems