Scaled Submicron Field-Plated Enhancement Mode High-K Gallium Nitride Transistors on 300mm Si(111) Wafer with Power FoM (R<sub>ON</sub> xQ<sub>GG</sub>) of 3.1 mohm-nC at 40V and f<sub>T</sub>/f<sub>MAX</sub> of 130/680GHz
Han Wui Then, M. Radosavljević, Pratik Koirala, Michael Beumer, Samuel James Bader, Ahmad Zubair, T. Hoff, R. Jordan, Thoe K. Michaelos, J. Peck, Ibrahim Ban, N. Nair, Heli Vora, K. Joshi, Inanc Meric, A. Oni, Nachiket Desai, Harish K. Krishnamurthy, K. Ravichandran, Jian Yu, S. Beach, Dimitri Frolov, A. Hubert, Alvaro D. Latorre-Rey, Said Rami, Jag Rangaswamy, Qiang Yu, P. Fischer
Abstract
We demonstrate a high voltage enhancement-mode (E-mode) high-k GaN-on-300mm Si(111) NMOS transistor capable of best-in-class performance and figure-of-merits for integrated power electronics and RF mm-wave. Using scaled submicron-length field-plate, the high-voltage GaN NMOS transistors demonstrate excellent R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> <675Ω·μm with BV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> up to 100V, and power figure-of-merit (FoM), R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> xQ <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GG</inf> of 3.1 mohm-nC at 40V with a projected lifetime of 10 years. This FoM at 40V is ~20X better than state-of-the-art e-mode p-GaN HEMT, and ~30X better than Si LDMOS. Both gate field-plated and source field-plated GaN NMOS demonstrate true emode operation, achieving drain leakages as low as 0.3pA/μm at 40V with V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> =0V, and can be fully turned on with V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> of 2V with low gate leakage <2pA/μm (as opposed to 5-6V required for pGaN HEMT), thus requiring only simple CMOS driver technology. A 2x2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> power GaN die comprising high-side and low-side switches with integrated clamps, is also fabricated. The low-side GaN NMOS switch has a total width of 1300mm, and R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSON</inf> of 1.9 mohm-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Moreover, the same 300mm GaN-on-Si(111) technology of this work, demonstrates a record f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf> of 680GHz (with f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> =130GHz) at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> =16V for a 30nm channel length GaN transistor employing scaled 100nm-length source field-plate.