<i>p</i>-Type High-Performance WSi<sub>2</sub>N<sub>4</sub> MOSFETs with the Ultrashort Scale of Sub-5 nm
Xianghe Liu, Yuliang Mao
Abstract
In this article, we explore the ballistic transport limits of p- and n- type monolayer (ML) WSi 2 N 4 metal-oxide-semiconductor field-effect transistors (MOSFETs) at the sub-5 nm scale. The results show that varying the doping concentration, gate length, and underlap region ( L UL ) structure can effectively tune the on - state current ( I on ) and subthreshold swing (SS) of the WSi 2 N 4 MOSFETs. Notably, I on, delay time (τ), and power dissipation (PDP) of the optimized p- type WSi 2 N 4 MOSFETs still fulfill the high-performance standard of the International Technology Roadmap for Semiconductors for 2028 until the gate length is minimized to 3 nm. I on of p- type WSi 2 N 4 MOSFETs with L g = 5 nm and L UL = 2 nm can be up to 1546 μA/μm. Meanwhile, the SS reaches exactly the thermal limit of 60 mV/dec. We also find that the use of high -k dielectric layers can significantly improve I on and SS of p- and n- type WSi 2 N 4 MOSFETs. Particularly, under the high- k dielectric layer, I on of p -type WSi 2 N 4 transistor with gate length L g = 3 nm without an underlap region is as high as 1550 μA/μm, which is considerably higher than that of other 2D material MOSFETs at the same scale. This work suggests that ML WSi 2 N 4 is highly prospective in the development of p -type high-performance transistors.