CMOS Ternary Logic With a Biristor Threshold Switch for Low Static Power Consumption
Joon‐Kyu Han, Ji‐Man Yu, Seo-Yeon Nam, Yang‐Kyu Choi
Abstract
A CMOS ternary logic is demonstrated using a biristor threshold switch (BTS). A biristor, which can operate as a threshold switch, encloses a two-terminal n-p-n structure with a floating p-base region akin to a base-open BJT. The switching mechanism is a single-transistor latch (STL). When a BTS and a MOSFET are serially connected, three stable states are sustained for a ternary logic system. Compared to other ternary devices, static power can be greatly reduced due to low leakage current of the BTS. In addition, the BTS and the MOSFET were co-integrated due to their homeomorphy for fabrication simplicity, i.e., because the BTS has a structure identical to that of a MOSFET, unlike other threshold switches.