Spiking Neuron Hardware-Level Fault Modeling
Sarah A. El-Sayed, Theofilos Spyrou, Antonios Pavlidis, Engín Afacan, Luis A. Camuñas-Mesa, B. Linares-Barranco, Haralampos‐G. Stratigopoulos
Abstract
The deployment of Artificial Intelligence (AI) hardware accelerators in a variety of applications, including safety-critical ones, requires assessing their inherent reliability to hardware-level faults and developing cost-effective fault tolerance techniques. This entails performing large-scale fault simulation experiments. However, transistor-level fault simulation is prohibitive and fault simulation should be carried out at a higher abstraction level. In this work, we focus on spiking neural networks (SNNs), and we follow a bottom-up approach starting from transistor-level simulations for developing a neuron behavioral-level fault model that can be readily employed for performing behavioral-level fault simulation of deep SNNs.