Role of Oxygen Deficiencies on the Stability of Indium Tin Oxide (ITO) Transistors
Sumaiya Wahid, Kasidit Toprasertpong, Mahnaz Islam, Aravindh Kumar, Muhammed Ahosan Ul Karim, Harsono Simka, H.‐S. Philip Wong, Eric Pop
Abstract
We investigate the threshold voltage (VT) stability of indium tin oxide (ITO) transistors under positive gate bias stress, comparing the performance of Al<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectrics. We attribute the unusual negative <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> shift (Δ<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> < 0 V) of our top-gated devices to oxygen scavenging by the dielectric. Notably, devices with Al<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> dielectric achieve median |Δ<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub>| ≤ 10 mV at room temperature, ~10× lower than devices with HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>, highlighting the significant influence of the dielectric layer. We also demonstrate that opposing effects of the top and bottom gates in a dualgated transistor can be used to attain a median |Δ<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub>| ≈ 150 mV with 2 V gate stress voltage, at elevated temperature (85 °C), which is ~3× lower than the top-gated devices under identical stress conditions.