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A 120-GHz Class-F Frequency Doubler With 7.8-dBm P<sub>OUT</sub> in 55-nm Bulk CMOS

Zhen Yang, Kaixue Ma, Fanyi Meng, Bing Liu

2023IEEE Journal of Solid-State Circuits21 citationsDOI

Abstract

This article analyzes the 2nd-order harmonic power generation with power level boosted by fundamental and 3rd-order harmonic based on the Krummenacher–Vittoz (EKV) models. The optimal waveforms of fundamental and 3rd-order harmonic are derived for maximizing the 2nd-order harmonic power. Adopting this method, a class-F frequency doubler in a 55-nm bulk CMOS technology is designed, fabricated, and measured. The doubler prototype achieves a 3-dB operation bandwidth of 112–125 GHz, a maximum output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {OUT}}$ </tex-math></inline-formula> ) of 7.8 dBm, a maximum conversion gain (CG) of −0.46 dB, a maximum efficiency of 6.8% with dc power consumption of 88 mW, and a core area of only 0.13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To the best of our knowledge, the proposed class-F doubler achieves the highest <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {OUT}}$ </tex-math></inline-formula> among similar CMOS works and is comparable to those in advanced SiGe technologies.

Topics & Concepts

CMOSFrequency multiplierdBmNotationPower (physics)HarmonicOrder (exchange)Electrical engineeringMathematicsPhysicsEngineeringArithmeticQuantum mechanicsEconomicsAmplifierFinanceRadio Frequency Integrated Circuit DesignMicrowave Engineering and WaveguidesAdvanced Power Amplifier Design
A 120-GHz Class-F Frequency Doubler With 7.8-dBm P<sub>OUT</sub> in 55-nm Bulk CMOS | Litcius