Scaling behavior of InAlN/GaN HEMTs on silicon for RF applications
Peng Cui, Yuping Zeng
Abstract
Abstract Due to the low cost and the scaling capability of Si substrate, InAlN/GaN high-electron-mobility transistors (HEMTs) on silicon substrate have attracted more and more attentions. In this paper, a high-performance 50-nm-gate-length InAlN/GaN HEMT on Si with a high on/off current ( I on / I off ) ratio of 7.28 × 10 6 , an average subthreshold swing (SS) of 72 mV/dec, a low drain-induced barrier lowing (DIBL) of 88 mV, an off-state three-terminal breakdown voltage ( BV ds ) of 36 V, a current/power gain cutoff frequency ( f T / f max ) of 140/215 GHz, and a Johnson’s figure-of-merit (JFOM) of 5.04 THz V is simultaneously demonstrated. The device extrinsic and intrinsic parameters are extracted using equivalent circuit model, which is verified by the good agreement between simulated and measured S- parameter values. Then the scaling behavior of InAlN/GaN HEMTs on Si is predicted using the extracted extrinsic and intrinsic parameters of devices with different gate lengths ( L g ). It presents that a f T / f max of 230/327 GHz can be achieved when L g scales down to 20 nm with the technology developed in the study, and an improved f T / f max of 320/535 GHz can be achieved on a 20-nm-gate-length InAlN/GaN HEMT with regrown ohmic contact technology and 30% decreased parasitic capacitance. This study confirms the feasibility of further improvement of InAlN/GaN HEMTs on Si for RF applications.