A Gate-All-Around Oxide Semiconductor FETs With Selectively Crystallized InGaOₓ Channel for Performance and Reliability Improvement
Ki-Woong Park, Anlan Chen, Kota Sakai, Sunbin Hwang, Xingyu Huang, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi
Abstract
In this article, we report performance enhancement and reliability improvement of oxide semiconductor FETs (OS FETs) by polycrystalline Ga-doped InO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> (poly-IGO). Atomic layer deposition (ALD) and post-deposition annealing (PDA) were employed to achieve crystallization of IGO. A systematic study of bottom-gate (BG) FETs with varied Ga concentrations and film thicknesses identified optimized conditions yielding a mobility up to 81 cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sup>/V ⋅ s. Low-temperature measurements were conducted to physically understand the mobility improvement. The carrier transport mechanisms were discussed. Then, we developed a novel selective crystallization method in the OS stack for process integration and device operation of gate-all-around (GAA) nanosheet (NS) IGO FETs. The fabricated GAA IGO FETs showed normally-OFF operation, high ON-current of 326 μA/μm, and a steep subthreshold slope of 68 mV/dec. In addition, GAA NS FETs exhibited further improved bias stress stability. This work provides a scalable strategy of poly-OS channels for monolithic 3-D (M3D) integration and 3-D memory such as 3-D DRAM and 3-D NAND.