Heterogeneous Integration of BEOL Logic and Memory in a Commercial Foundry: Multi-Tier Complementary Carbon Nanotube Logic and Resistive RAM at a 130 nm node
Tathagata Srimani, G.W. Hills, Mindy D. Bishop, C.L. Lau, Pritpal S. Kanhaiya, Rebecca Ho, A.H. Amer, Mango C.-T. Chao, Andrew Yu, Andrew Wright, A. Ratkovich, D. Aguilar, A. Bramer, C. Cecman, A. Chov, Gregory A. Clark, G. Michaelson, M. Johnson, Kyle Kelley, Patricia Manos, Khalil MI, Usman Suriono, S. Vuntangboon, Huijun Xue, Jefford Humes, Stênio Sã Rosário Furtado Soares, Brian Jones, S. Burack, ARVIND ARVIND, Anantha P. Chandrakasan, Bryan W. Ferguson, Matthew D. Nelson, Max M. Shulaker
Abstract
The inevitable slowing of two-dimensional scaling is motivating efforts to continue scaling along a new physical axis: the 3 <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</inf> dimension. Here we report back-end-of-line (BEOL) integration of multi-tier logic and memory established within a commercial foundry. This is enabled by a low-temperature BEOL-compatible complementary carbon nanotube (CNT) field-effect transistor (CNFET) logic technology, alongside a BEOL-compatible Resistive RAM (RRAM) technology. All vertical layers are fabricated sequentially over the same starting substrate, using conventional BEOL nano-scale inter-layer vias (ILVs) as vertical interconnects (e.g., monolithic 3D integration, rather than chip-stacking and bonding). In addition, we develop the entire VLSI design infrastructure required for a foundry technology offering, including an industry-practice monolithic 3D process design kit (PDK) as well as a complete monolithic 3D standard cell library. The initial foundry process integrates 4 device tiers (2 tiers of complementary CNFET logic and 2 tiers of RRAM memory) with 15 metal layers at a ~130 nm technology node. We fabricate and experimentally validate the standard cell library across all monolithic 3D tiers, as well as a range of sub-systems including memories (BEOL SRAM, 1T1R memory arrays) as well as logic (including the compute core of a 16-bit microprocessor) - all of which is fabricated in the foundry within the BEOL interconnect stack. All fabrication is VLSI-compatible and leverages existing silicon CMOS infrastructure, and the entire design flow is compatible with existing commercial electronic design automation tools.