Degradation Analysis of Planar, Symmetrical and Asymmetrical Trench SiC MOSFETs Under Repetitive Short Circuit Impulses
Renze Yu, Saeed Jahdi, Phil Mellor, Li Liu, Juefei Yang, Chengjun Shen, Olayiwola Alatise, Jose Ortiz Gonzalez
Abstract
In this article, the reliability of planar, symmetrical, and asymmetrical trench SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is analysed under repetitive short circuit impulses at 300 and 450 K. Both static and dynamic parameters are measured to characterize the degradation pattern of the three <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> structures. The degradation mechanisms are analyzed and the internal electro-thermal behavior of <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is revealed through TCAD models. It has been found out that there is minor degradation for planar SiC devices under both test conditions. The symmetrical trench SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> has the lowest reliability, which fails after 200 and 80 cycles at room and elevated temperature. The asymmetrical trench SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> has slightly higher reliability, failing after 1500 cycles and 500 cycles at room and elevated temperature, respectively. A comprehensive range of measurements until failure and the corresponding Silvaco TCAD analysis confirms that for both trench SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s, the deterioration of the gate oxide is responsible for the degradations and device failure. The higher the temperature, the higher electro-thermo-mechanical stress the devices suffer.