Cryogenic CMOS RF Device Modeling for Scalable Quantum Computer Design
Zhidong Tang, Zewei Wang, Ao Guo, Linlin Liu, Chengwei Cao, Xin Luo, Weican Wu, Yingjia Guo, Zhenghang Zhi, Yongqi Hu, Yongfeng Cao, Ganbing Shang, Liujiang Yu, Shaojian Hu, Shoumian Chen, Yuhang Zhao, Xufeng Kou
Abstract
This paper presents experimental RF characterizations and modeling on the nano-scale multi-finger gate MOSFETs of the HLMC 40 nm low-power CMOS technology. Both the resistive and capacitive components in the equivalent circuit model for the RF MOSFET devices are calibrated based on temperature-dependent S-parameter measurements (0.25 – 40 GHz) from 298 K to 6 K. By integrating the intrinsic device model and the extrinsic parasitic parameters, a generic cryogenic device RF model is developed to capture the cutoff frequency and high-frequency performance of NMOS and PMOS transistors with varied device configurations. The establishment of validated database as functions of device size, temperature, and frequency responses lays a solid foundation for practical large-scale cryo-CMOS RF circuit design and optimization.