Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection
Thibaut Marty, Tomofumi Yuki, Steven Derrien
2020IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems30 citationsDOIOpen Access PDF
Abstract
In this article, we propose a technique for improving the efficiency of convolutional neural network hardware accelerators based on timing speculation (overclocking) and fault tolerance. We augment the accelerator with a lightweight error detection mechanism to protect against timing errors in convolution layers, enabling aggressive timing speculation. The error detection mechanism we have developed works at the algorithm-level, utilizing algebraic properties of the computation, allowing the full implementation to be realized using high-level synthesis tools. Our prototype on ZC706 demonstrated up to 60% higher throughput with negligible area overhead for various wordlength implementations.
Topics & Concepts
Computer scienceOverhead (engineering)Convolution (computer science)Convolutional neural networkComputationError detection and correctionImplementationThroughputAlgorithmFault toleranceComputer engineeringParallel computingFault detection and isolationArtificial neural networkArtificial intelligenceDistributed computingWirelessProgramming languageTelecommunicationsActuatorOperating systemAdvanced Memory and Neural ComputingRadiation Effects in ElectronicsFerroelectric and Negative Capacitance Devices