A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO
Yeonggeun Song, Han-Gon Ko, Changhyun Kim, Deog‐Kyoon Jeong
Abstract
This brief presents an all-digital PLL (AD-PLL) for a DDR5 registering clock driver (RCD) with a self-biased supply-noise-compensation (SNC) technique. By combining two Nagata current sources that have opposite dependency on supply variations, it offers a constant current to a ring oscillator over a wide range of supply voltage. Thereby, the dynamic voltage droop due to variations in workload is compensated while a voltage margin for mass production is improved. Since the SNC technique operates independently of the PLL loop bandwidth without using feedback, the proposed AD-PLL is free from the stability problem associated with bandwidth overlapping. Quantitative analyses on static and dynamic characteristics of the proposed SNC technique and relevant design considerations are addressed. Fabricated in the 28-nm CMOS technology, the AD-PLL occupies an active area of 0.06 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 12.1 mW at 3.0 GHz with a 1.1 V supply voltage. The power-supply-noise-attenuation (PSNA) is measured as 40 dB and the integrated rms jitter of 271 fs is observed.