Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits
Yun Zhou, S. C. Song, Halil Kükner, Giuliano Sisto, Sheng Yang, Anita Farokhnejad, Mohamed Naeim, Moritz Brunion, Ji-Yung Lin, Odysseas Zografos, Pieter Weckx, S. Ekbote, Nick Stevens-Yu, D. Greenlaw, Steve Molloy, Geert Hellings, Julien Ryckaert
Abstract
We evaluate block-level power-performance-area (PPA) tradeoffs of two backside power (BSPDN) options: Through Silicon Via in the Middle of Line (TSVM) and Backside Contact (BSC) in an A10 (10A) nanosheet technology node. The benchmarking was conducted for high-performance designs in both high-performance and high-density technology scenarios taking the traditional frontside power option as the baseline. HP technology clearly benefits most since its dense PDN consumes a lot of metal routing resources on the frontside to keep an acceptable IR-drop. Introducing BSPDN frees up those metals for more efficient signal routing, resulting in 19% smaller area (8% for HD). Continued standard cell scaling by means of BSC translates into a further -25% core area, with only the densest 4.5T HD results showing signs of congestion at high frequencies.