A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With −101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction
Muhammed Bolatkale, Robert J. Rutten, Hans Brekelmans, Shagun Bajoria, Yihan Gao, B. Burdiek, Lucien J. Breems
Abstract
In this article, a 6-GHz, 2-bit, fourth-order continuous-time delta–sigma (CT <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ) analog-to-digital converter (ADC) fabricated in 28-nm CMOS is presented. It achieves −101- and −105-dBc total harmonic distortion (THD)/third-order inter-modulation (IM3) typically and 72.3-dB signal to noise and distortion ratio (SNDR) in 120-MHz bandwidth (BW). The ADC comprises four cascaded integrators with inverter-based amplifiers, an offset compensated 2-bit quantizer, and calibrated 2-bit feedback (FB) digital-to-analog converter (DAC). The DAC and quantizer employ blind digital calibration techniques enabling the wideband linearity performance. The ADC does not require any external test signal during calibration. The power dissipation of the modulator core, including demultiplexer, is 108.8 mW.