Investigation of the Off-State Degradation in Advanced FinFET Technology—Part II: Compact Aging Model and Impact on Circuits
Zixuan Sun, Zirui Wang, Runsheng Wang, Lining Zhang, Jiayang Zhang, Zuodong Zhang, Jiahao Song, Da Wang, Zhigang Ji, Ru Huang
Abstract
Part I of this article revealed that the OFF-state degradation consists of both bias temperature instability (BTI) and hot carrier degradation (HCD) traps in different channel regions. In part II of this article, a compact aging model of OFF-state degradation in advanced FinFETs is developed and validated by silicon data of 7-nm node, including the degradation and recovery phases. The model is capable to cover various types of devices, such as n/p types, core/IO devices, with short/long-channels. Meanwhile, trap contributions over time in different types of FinFETs are discussed based on the model component analysis. The model is implemented into circuit simulators and used to predict circuit aging with OFF-state degradation, for example, a ring oscillator (RO) circuit. The extrapolation result shows that up to 25% degradation is underestimated if the OFF-state reliability is not considered. This work provides a solution for more accurate reliability evaluation of nanoscale circuit design.