Improved Multi-bit Statistics of Novel Dual-gate IGZO 2T0C DRAM with In-cell V<sub>TH</sub> Compensation and ΔV<sub>SN</sub>/ΔV<sub>DATA</sub> Boosting Technique
Kaifei Chen, Zhengyong Zhu, Wendong Lu, Menggan Liu, Fuxi Liao, Zijing Wu, Jiebin Niu, Bok-Moon Kang, Dan Wang, Xie-Shuai Wu, Mingxu Liu, Yong Yu, Nan Yang, Guilei Wang, Kan-Yu Cao, Lingfei Wang, Di Geng, Nianduan Lu, Guanhua Yang, Chao Zhao, Arokia Nathan, Ling Li, Ming Liu
Abstract
For the first time, one novel dual-gate IGZO DRAM is proposed and demonstrated for multi-bit storage. Contrary to traditional 2T0C, the data is written into storage node through both write and read transistors, achieving novel in-cell V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> compensation without increasing bit-cell complexity. The optimized read transistor with positive V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> and high on-state current enables efficient V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> compensation with sub-10 ns writing speed. Meanwhile, owing to V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> modulation by additional gate of read transistor, great boost of differential voltage written into storage node (SN) is shown, with a record-high ratio (ΔV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SN</inf> /ΔV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DATA</inf> ) of 1.46. By this design, 3-bit storage among 25 cells exhibits improved statistical distribution with one order reduction of standard deviation. This work paves the forward way for multi-bit IGZO 2T0C DRAM applications.